A semiconductor device, particularly a semiconductor device including a bipolar transistor, is suitable to design an analog circuit due to characteristics of a bipolar transistor, such as high load driving force, high speed, low noise and the like.
FIG. 14 is a schematic cross-sectional view of a semiconductor device including a conventional bipolar transistor, and in this example a vertical npn bipolar transistor is formed on a silicon semiconductor substrate 100.
This semiconductor substrate 100 has on a p-type silicon substrate 101 a structure in which an n-type silicon semiconductor layer 102 has been grown epitaxially.
An n-type collector buried region 103 is formed in the substrate 101.
A separating and insulating layer 104 which separates a portion where the bipolar transistor is formed from the other portion is formed on the surface of the semiconductor layer 102 by means of LOCOS (Local Oxidation of Silicon).
Also, under the separating and insulating layer 104 element separating regions 105 which execute element separation by p-n junction are formed by ion implantation surrounding the portion where the bipolar transistor is formed.
Further, a window portion where the separating and insulating layer 104 is not formed is provided on the collector buried region 103, and an n-type plug-in region 106 having the depth that reaches the collector buried region 103, into which highly concentrated n-type impurities are ion-implanted, is formed under the window portion. Also, a highly concentrated collector electrode take-out region 107 is formed on the surface of this plug-in region 106.
A collector region 108 composed of a part of the n-type semiconductor layer 102 is formed on the collector buried region 103.
Also, a first insulating layer 111 made of SiO2 is formed on the entire surface of the substrate 100 at first; and then an opening 111W is provided in this insulating layer 111, through which impurities are doped to form a collector highly concentrated region 109.
Across the inside of this opening 111W and on the first insulating layer 111, a base semiconductor layer 112 composed of a silicon semiconductor layer constituting an intrinsic base region and a base electrode take-out region is deposited.
This base semiconductor layer 112 is entirely deposited at first and then a requiring pattern is formed by pattern etching of means of photolithography.
Additionally, regarding this base semiconductor layer 112, the part deposited on the surface of the semiconductor substrate 100, namely, the part deposited directly on the semiconductor layer 102 is deposited as a epitaxially grown single-crystal layer, and the part formed on the first insulating layer 111 is deposited as a polycrystalline layer.
Further, a second insulating layer 113 made of SiO2 is entirely formed covering the base semiconductor layer 112 at first; and then an opening 113W is provided in the base semiconductor layer 112, through which impurities are doped to form a collector portion 110.
Then, an emitter semiconductor layer 114 made of an n-type silicon semiconductor layer is deposited including the inside of the opening 113W.
This emitter semiconductor layer 114 is also entirely deposited at first and then patterned accordingly by pattern etching by means of photolithography. Specifically, as shown in FIG. 14, a photoresist layer 115 is patterned on the portion where the emitter semiconductor layer 114 is formed by coating a photoresist layer, pattern exposure, and development, as intended. With this photoresist layer 115 serving as an etching mask, the emitter semiconductor layer 114 is etched so as to be patterned accordingly, namely patterned to have a portion that is in connect with the base semiconductor layer 112 through the opening 113W and an extending portion 114H of an requiring width on the peripheral part of the opening 113W.
After that, as shown in FIG. 15, with the photoresist layer 115 serving as an etching mask, the second insulating layer 113 in FIG. 14 is etched by anisotropic etching, and the base take-out region of the base semiconductor layer 112 other than the portion in contact with the emitter semiconductor layer 114 is exposed to the outside.
On this occasion, intercalated insulating layers 113S1 and sidewalls 113S2 where the second insulating layer 113 remains are formed under the extending portion 114H of the emitter semiconductor layer 114 and on the outer end surface of the base semiconductor layer 112, respectively; as regards the etching performed on the insulating layer 113, overetching is executed in order for the surface of the base semiconductor layer 112 to be exposed without fail, so that later-mentioned metal salicide can be formed.
Subsequently, the photoresist 115 is removed, and a metal layer such as Ti or Co is, for example, sputtered on the entire surfaces of the base semiconductor layer 112 and the emitter semiconductor layer 114 exposed to the outside and heat treatment is performed, whereby only at the parts where this metal layer is directly deposited on the semiconductor layers 112 and 114 a low-resistance metal silicide layer 116 is formed by reaction of the metal and Si, as shown in FIG. 16.
After that, a planarizing and insulating layer 117 made of BPSG (Boron Phosphorus Silicate Glass) or the like is entirely formed.
A Contact through-hole 118 is provided in each of: the planarizing and insulating layer 117 on the metal silicide layer 116, one portion of which is on the base take-out region portion of the base semiconductor layer 112 and the other portion of which is on the emitter semiconductor layer 114, and also the planarizing and insulating layer 117 and the insulating layer 111 on the collector take-out region 107; and these contact through-holes 118 are each filled with electrodes made by filling conductive plugs with tungsten (W) or the like, that is to say, a base electrode 119B, an emitter electrode 119E, and a collector electrode 119C. In such manner, each of the electrodes 119B, 119E, and 119C has ohmic contact to the base take-out region portion of the base semiconductor layer 112 and the emitter semiconductor layer 114. On the other hand, a conductive layer 120 constituting wiring or electrodes formed on the planarizing and insulating layer 117 is contacted to each of those electrodes 119B, 119E and 119C.
As described above, a semiconductor integrated circuit device, in which as a circuit element a vertical bipolar transistor consisting of the collector portion 110 and the base and emitter regions made of the base semiconductor layer 112 and the emitter semiconductor layer 114 is formed, is constructed.
The aforementioned semiconductor device including a conventional bipolar transistor and the method for manufacturing thereof include the formation of a metal silicide layer; however, in this case, there are problems in forming a metal silicide layer at the target positions accurately and appropriately so that a reliable semiconductor device is obtained.
First of all, regarding the aforementioned conventional manufacturing method, the insulating layer 113 on the base semiconductor layer 112 shown in FIG. 14 is removed, and in the operation in which the base semiconductor layer 112 is exposed to the outside as shown in FIG. 15, etching onto the insulating layer 111 needs to be overetching in order for the base semiconductor layer 112 to be exposed without fail to the outside as mentioned above.
The amount of such overetching is generally required to be the amount corresponding to, for example, approximately 50% of the thickness of the second insulating layer 113.
Such overetching unavoidably gives restrictions when each of the film thicknesses of the first and second insulating layers 111 and 113 is selected.
Specifically, it is necessary to make the aforementioned first insulating layer 111 thicker or to make the second insulating layer 113 thinner.
However, increase in the film thickness of the first insulating layer 111 makes the unevenness at the peripheral part of the opening 111W of the base semiconductor layer 112 greater, so that inconvenience arises in which stress is greatly concentrated at that part.
Also, contrary to this, decrease in the film thickness of the second insulating layer 113 makes the height of the intercalated insulating layer 113S1 of the emitter semiconductor layer 114 diminished, so that parasitic capacitance between the extending portion 114H of the emitter layer 114 and the base semiconductor layer 112 which oppose each other with this intercalated insulating layer 113S1 in between increases, thereby hindering high-speed operation.
Additionally, regarding the construction in FIG. 16, since the metal silicide layer 116 is formed on the base and emitter semiconductor layers 112 and 114, electrode contact resistance thereto can be reduced. However, when taking out an electrode from the collector, since the collector take-out region 107 is provided without forming a metal silicide layer, contact resistance to the collector can not be reduced sufficiently.
Since this contact resistance to the collector is a factor which decides the saturation voltage VCE(sat) between a collector and an emitter of the bipolar transistor and the current gain, that is, the current capacity, with which the gain hFE of the transistor begins to decrease and with which the cutoff frequency fTmax and the maximum vibration frequency fmax begin to decrease, it is desirable that the contact resistance to the collector be reduced as much as possible in terms of low-voltage operation and high driving capability.
As mentioned above, in order to reduce the contact resistance to the collector, the cross-sectional area of the collector electrode 119C can be made large; in this case, however, the area for the collector electrode becomes large, so that a number of inconveniences such as decrease in the degree of integration, cost rise, and deterioration in the high-frequency characteristics due to the increase in the parasitic capacitance of the transistor are made to occur.
Also, regarding metal silicide, metal layers may easily remain in a stringer-like manner at the edge of the base semiconductor layer 112 of the above bipolar transistor, and this metal exfoliates in the production process or the like of the semiconductor device, thereby causing a short circuit between elements or wirings, for example.
This means that, in the case of the conventional structure shown in FIG. 16, since the metal layer is directly deposited on the end surface of the emitter semiconductor layer 114, the metal silicide layer 116 is formed across the entire surface; however, regarding the base semiconductor layer 112, the sidewall 113s2 made by the insulating layer 113 exists at the end surface thereof and unevenness is created, so that the metal layer tends to remain in a stringer-like manner from the shoulder portion at the edge to the uneven part of the base semiconductor layer 112, and this becomes a reason for a short circuit by exfoliation as mentioned above, causing deterioration in the yield rate, reliability and the like.